C2V process engineers and operators work in a 1030 sqm 4" cleanroom facility, where the wafers are handled in a class 100 environment. The cleanroom is fully equipped with all necessary apparatus and process facilities. The largest part of the cleanroom is dedicated to Micro System Technology to make MEMS devices.

Main Capabilities

Technology

• Surface, bulk & SOI silicon micromachining
• Wet and (high aspect ratio) dry etching
• Mask generation· aligned wafer bonding
• Thin layer deposition· ion beam implantation
• Fluidic Multi Chip Modules
• Nano patterning

Analysis

• AFM/STM, SEM/EDX
• XRD, AES, XPS, TEM
• Surface profiling
• Ellipsometry
• Resistivity mapping
• Circuit and device characterization

Design

• Dedicated mask design software
• Integrated software BPM and mode solvers
• Printed Circuit lay-out
• 2D and 3D CAD

Testing

• Standard IC test facilities
• Mixed signal testing
• Process-control module testing
• Microsystem debugger with an electron-beam-prober
• Dedicated functional test set-ups